This paper is intended to investigate the impact of structural parameters (in particular: body thickness (TBody), Source/Drain Length (LS /LD) and gate oxide thickness (TOX)) on the electrical characteristics of nanoscale Double Gate SOI MOSFET (DG SOI MOSFET) in subthreshold regime. It will be shown that a reduction in Ls /Ld doesn’t have a profound effect on both on-current and Drain Induced Barrier Lowering Effect (DIBL); however it increases the effective Gate Capacitance (CGeff) significantly. A decrease in Tbody results in an increase in CGeff and a decrease in potential barrier height while ION is reduced.This investigation also proves that as TOX is increased, CGeff is decreased. A decline in TOX reduces ION while it drastically increases ION /IOFF ratio.

Silicon carbide power devices are widely utilized in applications requiring high voltage and current. Due to the limited current capability of a single module, silicon carbide MOSFETS are frequently arranged in parallel to enhance the current capacity of the final product. However, variations in circuit parameters or inconsistencies in semiconductor manufacturing can cause imbalances in the current among the parallel modules, potentially resulting in performance and dependability challenges. To tackle the matter, this paper introduced the use of an active approach designed for paralleled SiC MOSFETS to resolve these unbalanced currents. The proposed method used a current transformer to detect the imbalance current. Further, an active compensator is presented within a closed-loop control feedback that effectively eliminates the current imbalance among parallell modules in a master-slave configuration. Details of current transformer and stability of the closed-loop control are investigated. Experimental results are provided to showcase the viability and efficiency of the proposed approach.

In this paper, a nonlinear model for the body resistance of a 45nm PD SOI MOSFET is developed. This model verified on the base of the small signal three-dimensional simulation results. In this paper by using the three-dimensional simulation of ISE-TCAD software, the indicating factors of body resistance in nanometer transistors and then are shown, using the surface potential model. A mathematical relation to calculat the body resistance incorporating device width and body potential was derived. Excellent agreement was obtained by comparing the model outputs and threedimensional simulation results.

A simple general-purpose I-V model for all operating modes of deep-submicron MOSFETS is presented. Considering the most dominant short channel effects with simple equations including few parameters, a reasonable trade-off between simplicity and accuracy is established. To further improve the accuracy, model parameters are optimized over various channel widths and full ranges of operating voltages using a heuristic optimization algorithm. The obtained results demonstrate only 1. 28% and 0. 97% average error in IBM 0. 13um CMOS technology node for NMOS and PMOS, respectively, comparing with the accurate physically-based BSIM3 model. Furthermore, the tolerance of the model accuracy against parameters variation is investigated.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) plays a key role in electronic industry in recent years. Among MOSFETS, double gate (DG) transistor is an important device. During last decade, many efforts have been accomplished to improve the device properties. A new structure of the double gate (DG) transistor on SOI technology is proposed in this paper. In SOI technology, buried oxide as insulating layer has lower thermal conductivity than silicon and makes some problems for nano-scale MOSFETS. Incorporating a silicon window under the channel region and two spacers reduces maximum temperature of device. The simulation with ATLAS simulator shows that by optimizing the length and thickness of the silicon window, an acceptable device temperature would be achieved and makes the double gate structure more reliable for nano-scale applications at high temperature. Drain current, lattice temperature, electron mobility, hole density, threshold voltage, subthreshold swing and off current are improved in the new structure.

Influences of source and drain recess structures on SiGe epitaxy growth, SiGe step height, facet formation, ID, sat and resistance performance are investigated. Growth rate of SiGe height increases with decreased recess width at a fixed depth of 62 nm. Under a fixed recess width of 96.3 nm, the deeper the recess, the higher the growth rate of SiGe height. An increase in the depth/width ratio of the recessed Si geometry may promote SiGe {001} growth. Upon the recess, SiGe step height is influenced by the initial SiGe orientation. A longer {001} facet of SiGe initial orientation causes a higher growth rate of SiGe step height. Higher IDsat and lower resistance can be achieved by increasing SiGe volume with wider recess width, deeper recess depth, and higher SiGe step height.

The effects of the oxygen vacancies on the microscopic potential distribution and macroscopic potential averaged over one period around the defect for silicon dioxide have been investigated via first-principles calculations. The results demonstrate that such an effect is limited to the dimensions of one cell. Detailed analysis of the planar macroscopic average potential shows that the conduction band alignment caused by the defect and its effects on the tunneling currents have been calculated. The calculations demonstrate that the relative increase in the electron direct tunneling current caused by the oxygen vacancy depends on the position of oxygen vacancy. It is also shown that the increase in the direct tunneling current caused by the oxygen vacancy exponentially decreases with increasing oxide thickness, whereas its relative increase changes little.

In this paper the method of sensorless startup of direct current brushless motor using third harmonic back Electromotive Force (EMF) and motor startup using microcontroller for pulse width modulation, power switch control and motor output analysis is presented which renders RPM control and high speed achievement for motor. The microcontroller is used for processor and metal-oxide semiconductor field-effect transistor (MOSFETS) are used for power circuit. Besides, the motor does not have any sensors to detect rotor position. Furthermore, the microcontroller modulates pulse width, controls power circuit and analyses motor output. The innovation in this research is that the third harmonic function is used for motor control and is compared with the Back-EMF force to recognize zero crossing. Moreover, N-type MOSFETS are used in power circuit high side and low side which are useful in the current rate of MOSFETS due to their similarities. Also, the IR2101 MOSFET drive is utilized for startup which improves the firing time of MOSFETS. Besides, using tantalum capacitors and putting resistor by the gate route of MOSFETS is efficient. Finally, experimental results are given to verify the validation of the proposed method.

Wireless energy transfer is of high interest, and applications such as RFID, implantable devices, electric vehicles, and charging cell phones are widely used. Power dissipation of power MOSFETS used in these applications affect efficiency of such circuits. In this paper a special method has been used to lower energy dissipation of inverters and replace MOSFETS with energy storing elements in the circuit. In the new method two MOSFETS have been omitted from the inverter bridge circuit. A self-oscillating full-bridge MOSFET-inductor circuit with high efficiency and low power dissipation has been implemented with minimum component. The implemented circuit has 24% efficiency at 20cm distance for energy transfer.